Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs

@article{Sehgal2007OptimizationOD,
  title={Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs},
  author={A. Sehgal and K. Chakrabarty},
  journal={IEEE Transactions on Computers},
  year={2007},
  volume={56}
}
  • A. Sehgal, K. Chakrabarty
  • Published 2007
  • Computer Science
  • IEEE Transactions on Computers
  • The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive different channels at different data rates. Examples of such ATEs include the Agilent 93000 series tester based on port scalability and the test processor-per-pin architecture and the Tiger system from Teradyne. The number of tester channels with high data rates may be constrained in practice, however, due to ATE resource… CONTINUE READING
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