Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs

@article{Sehgal2007OptimizationOD,
  title={Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs},
  author={Anuja Sehgal and Krishnendu Chakrabarty},
  journal={IEEE Transactions on Computers},
  year={2007},
  volume={56}
}
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive different channels at different data rates. Examples of such ATEs include the Agilent 93000 series tester based on port scalability and the test processor-per-pin architecture and the Tiger system from Teradyne. The number of tester channels with high data rates may be constrained in practice, however, due to ATE resource… CONTINUE READING
Highly Cited
This paper has 18 citations. REVIEW CITATIONS

References

Publications referenced by this paper.
Showing 1-10 of 30 references

Tiger: Advanced Digital with Silicon Germanium Technology

  • Teradyne Technologies
  • http://www.teradyne.com/tiger/ digital.html, .
  • 2006
Highly Influential
3 Excerpts

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm

  • Y. Huang
  • Proc. IEEE Int’l Test Conf. (ITC), pp. 74-82, .
  • 2002
Highly Influential
5 Excerpts

Agilent 93000 Flexible Parallel Test Solution

  • Verigy
  • http:// www.verigy.com/content/dav/verigy…
  • 2006
1 Excerpt

Power Constrained Preemptive TAM Scheduling Test Scheduling with Power - Time Tradeoff and Hot - Spot Avoidance Using MILP

  • B. Al-Hashimi Rosinger, N. Nicolici
  • Proc . IEE Computers and Digital Techniques
  • 2004