Optimization of Delta-Sigma ADC for Column-Level Data Conversion in CMOS Image Sensors

Abstract

A delta-sigma analog-to-digital-converter (ADC) is designed, optimized and simulated for column-level data conversion in a CMOS image sensor. For a 0.18 mum process, the design achieves 80 dB of signal-to-noise ratio (SNR), including a 10 dB margin for kTC noise not simulated, and consumes 210 muW of power at a 50 kHz sampling rate. Low power is realized… (More)

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Cite this paper

@article{Mahmoodi2007OptimizationOD, title={Optimization of Delta-Sigma ADC for Column-Level Data Conversion in CMOS Image Sensors}, author={Ahmed Mahmoodi and Deepak Joseph}, journal={2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007}, year={2007}, pages={1-6} }