Optimization and process variation analysis of nano-scale transistors

Abstract

We utilize fully self-consistent quantum mechanical simulator based on Contact Block Reduction (CBR) method [1] to optimize 10 FinFET device to meet ITRS requirements for High Performance (HP) Double-Gate (DG) devices. Fin width, gate oxide thickness, and doping profile are chosen to reflect realistic values and to boost on-current while keeping the total… (More)

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