Advances in VLSI and optoelectronic multichip module technologiesare enabling the construction of ultracompact massively parallelprocessing systems. The technological parameters that define thewirability and delay characteristics of these technologies have asignificant impact on the system architecture. An analytical modelis presented that allows the design space exploration of theinterconnection networks associated with multinode chips packaged on asingle multichip module substrate. Possible system designs areevaluated for a two-level interconnect with separate k-aryn-cube networks for interchip and intrachipcommunication. The impact of several architectural andtechnological parameters on the optimal network implementation (based on average no-load latency) is analyzed.