Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time

@inproceedings{Tsai2003OptimalMZ,
  title={Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time},
  author={Jeng-Liang Tsai and Tsung-Hao Chen and Charlie Chung-Ping Chen},
  booktitle={ISPD},
  year={2003}
}
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-sizing problems have long been considered intractable. None of the existing approaches can guarantee optimality for general clock trees to the authors' best knowledge. In this paper, we present an ε-optimal zero-skew wire-sizing algorithm, ClockTune, which guarantees zero-skew with delay and area within ε distance to the… CONTINUE READING
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