Optimal memory controller placement for chip multiprocessor


In this paper, we analyze and compare different placements of memory controllers for Chip Multiprocessors (CMPs). As the number of cores increases, Network-on-Chip (NoC) based architectures are proposed as a promising interconnect technique for CMP. The memory bandwidth between on-chip components and off-chip memory has become a critical problem. The… (More)
DOI: 10.1145/2039370.2039405