Optimal manufacturable CNN array size for time multiplexing schemes

  title={Optimal manufacturable CNN array size for time multiplexing schemes},
  author={Gunhee Han and Jose Pineda de Gyvez and Edgar Sdnchez-Sinencio},
This paper presents a feasibility analysis to predict the optimal size of VLSI CNN implementations. A 3x3 CNN IC test prototype was designed and fabricated for this purpose. The study considers both the manufacturability and computing performance power of hypothetical large CNN arrays. The manufacturability analysis hus been geared towards IC yield prediction using our actual IC layout along with some realistic parameters representing the "cleanliness" of the manufmuring line. Additionally… CONTINUE READING

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