Optimal One-Bit Full Adders With Different Types of Gates
@article{Liu1974OptimalOF, title={Optimal One-Bit Full Adders With Different Types of Gates}, author={Tso-Kai Liu and Keith R. Hohulin and Lih-Er Shiau and S. Muroga}, journal={IEEE Transactions on Computers}, year={1974}, volume={C-23}, pages={63-70} }
Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder. Optimality is derined as the minimization of the number of gates under different restrictions.
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References
SHOWING 1-5 OF 5 REFERENCES
A Catalog of Three-Variable Or-Invert and And-Invert Logical Circuits
- Mathematics, Computer Science
- IEEE Trans. Electron. Comput.
- 1963
- 102
Design of Optimal Switching Networks by Integer Programming
- Mathematics, Computer Science
- IEEE Transactions on Computers
- 1972
- 37