Optimal One-Bit Full Adders With Different Types of Gates
@article{Liu1974OptimalOF, title={Optimal One-Bit Full Adders With Different Types of Gates}, author={Tso-Kai Liu and Keith R. Hohulin and Lih-Er Shiau and Saburo Muroga}, journal={IEEE Transactions on Computers}, year={1974}, volume={C-23}, pages={63-70} }
Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder. Optimality is derined as the minimization of the number of gates under different restrictions.
18 Citations
Parallel multipliers with NOR gates based on G-minimum adders
- Computer ScienceInternational Journal of Computer & Information Sciences
- 2004
The parallel multipliers of NOR gates are designed, by expressing two numbers to be multiplied in the sign and magnitude representation unlike those in Ref. 2, using fewer gates, fewer connections, and faster operation than conventional multiplier based on carry-save adders.
Minimum Parallel Binary Adders with NOR (NAND) Gates
- Computer ScienceIEEE Transactions on Computers
- 1979
The minimality of the number of NOR gates is proved for an arbitrary value of n and it is proved that the adders must be a cascade ofbasic modules and that there exist many different types of basic modules.
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Two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders are considered, with minimum tests for stuck-at-fault models, and it is proved that one of the full adders can be tested by only three test patterns for single stuck- at-faults.
Logic Networks of Carry–Save Adders
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The derived networks of carry–save adder modules (NOCSAM's) have the advantages of fewer gates, fewer connections, and faster operation.
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The derived networks of carry–save adder modules (NOCSAM's) have the advantages of fewer gates, fewer connections, and faster operation.
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Design of logic networks, in single-rail input logic, with a minimum number of NOR gates for parity functions of an arbitrary number of variables is described. This is partly based on minimum…
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FPGA-based synthesis results and case-study comparisons of the if-diagrambased adders to the BrentKung and majorityinvertor gate adders show that the new adder architecture leads to faster and smaller digital circuits.
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64-bit CLA is discussed and simulation results for 32bit and 64bit CLA has been exposed and the purposed design shows the Performance parameter chip area and delay in results.
Minimization of Logic Networks Under a Generalized Cost Function
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According to the computational results, for the majority of the functions the first type of minimal networks is identical to the second type, and for no function were networks of the third type found to exist.
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