Optimal One-Bit Full Adders With Different Types of Gates

  title={Optimal One-Bit Full Adders With Different Types of Gates},
  author={Tso-Kai Liu and Keith R. Hohulin and Lih-Er Shiau and Saburo Muroga},
  journal={IEEE Transactions on Computers},
Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder. Optimality is derined as the minimization of the number of gates under different restrictions. 

Parallel multipliers with NOR gates based on G-minimum adders

The parallel multipliers of NOR gates are designed, by expressing two numbers to be multiplied in the sign and magnitude representation unlike those in Ref. 2, using fewer gates, fewer connections, and faster operation than conventional multiplier based on carry-save adders.

Minimum Parallel Binary Adders with NOR (NAND) Gates

The minimality of the number of NOR gates is proved for an arbitrary value of n and it is proved that the adders must be a cascade ofbasic modules and that there exist many different types of basic modules.

On the adders with minimum tests

Two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders are considered, with minimum tests for stuck-at-fault models, and it is proved that one of the full adders can be tested by only three test patterns for single stuck- at-faults.

Logic Networks of Carry–Save Adders

The derived networks of carry–save adder modules (NOCSAM's) have the advantages of fewer gates, fewer connections, and faster operation.

Logic Networks of Carry-Save Adders

The derived networks of carry–save adder modules (NOCSAM's) have the advantages of fewer gates, fewer connections, and faster operation.

Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables

Design of logic networks, in single-rail input logic, with a minimum number of NOR gates for parity functions of an arbitrary number of variables is described. This is partly based on minimum

mAnAGement OF teCHniCAl OBJeCtS

FPGA-based synthesis results and case-study comparisons of the if-diagrambased adders to the BrentKung and majorityinvertor gate adders show that the new adder architecture leads to faster and smaller digital circuits.

Performance Analysis of 64-Bit Carry Look Ahead Adder

64-bit CLA is discussed and simulation results for 32bit and 64bit CLA has been exposed and the purposed design shows the Performance parameter chip area and delay in results.

Minimization of Logic Networks Under a Generalized Cost Function

According to the computational results, for the majority of the functions the first type of minimal networks is identical to the second type, and for no function were networks of the third type found to exist.

Redundancy check technique for designing optimal networks by branch-and-bound method

A redundancy check procedure is presented which is intended to reduce the computation time of the branch- and-bound algorithm for designing minimal NOR networks under various network constraints,



A Catalog of Three-Variable Or-Invert and And-Invert Logical Circuits

This report gives a complete catalog of minimal NOR circuits and minimal NAND circuits, assuming complements not available, for all logic functions of three variables. Minimal circuits for a function

Design of Optimal Switching Networks by Integer Programming

Various optimal networks are derived by a computer as follows: optimal NOR networks and optimal NOR-AND networks for all functions of up through three variables, one-bit adders with various gate types, and others, indicating the computational feasibility of the integer programming approach.

Logical Design of Optimal Digital Networks by Integer Programming

No efficient design method has been known for designing optimal networks with arbitrary types of gates under arbitrary network restrictions, except the exhaustive method, i.e., a method which exhausts all conceivable networks and chooses a best one.