Optimal One-Bit Full Adders With Different Types of Gates

@article{Liu1974OptimalOF,
  title={Optimal One-Bit Full Adders With Different Types of Gates},
  author={Tso-Kai Liu and Keith R. Hohulin and Lih-Er Shiau and Saburo Muroga},
  journal={IEEE Transactions on Computers},
  year={1974},
  volume={C-23},
  pages={63-70}
}
Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder. Optimality is derined as the minimization of the number of gates under different restrictions. 
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18 Citations
Background Citations
1
Methods Citations
2

18 Citations

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Logic Networks of Carry–Save Adders
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The derived networks of carry–save adder modules (NOCSAM's) have the advantages of fewer gates, fewer connections, and faster operation.
Logic Networks of Carry-Save Adders
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Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
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mAnAGement OF teCHniCAl OBJeCtS
TLDR
FPGA-based synthesis results and case-study comparisons of the if-diagrambased adders to the BrentKung and majorityinvertor gate adders show that the new adder architecture leads to faster and smaller digital circuits.
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64-bit CLA is discussed and simulation results for 32bit and 64bit CLA has been exposed and the purposed design shows the Performance parameter chip area and delay in results.
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