Optimal One-Bit Full Adders With Different Types of Gates

@article{Liu1974OptimalOF,
  title={Optimal One-Bit Full Adders With Different Types of Gates},
  author={Tso-Kai Liu and Keith R. Hohulin and Lih-Er Shiau and Saburo Muroga},
  journal={IEEE Transactions on Computers},
  year={1974},
  volume={C-23},
  pages={63-70}
}
Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder. Optimality is derined as the minimization of the number of gates under different restrictions. 
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18 Citations
Background Citations
1
Methods Citations
2

18 Citations

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Logic Networks of Carry-Save Adders

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References

SHOWING 1-5 OF 5 REFERENCES

A Catalog of Three-Variable Or-Invert and And-Invert Logical Circuits

This report gives a complete catalog of minimal NOR circuits and minimal NAND circuits, assuming complements not available, for all logic functions of three variables. Minimal circuits for a function…

Design of Optimal Switching Networks by Integer Programming

TLDR
Various optimal networks are derived by a computer as follows: optimal NOR networks and optimal NOR-AND networks for all functions of up through three variables, one-bit adders with various gate types, and others, indicating the computational feasibility of the integer programming approach.

Logical Design of Optimal Digital Networks by Integer Programming

TLDR
No efficient design method has been known for designing optimal networks with arbitrary types of gates under arbitrary network restrictions, except the exhaustive method, i.e., a method which exhausts all conceivable networks and chooses a best one.

An algorithm for nand decomposition of combinational switching functions

Threshold logic and its applications