# Optimal Combination of Number of Taps and Coefficient Bit-Width for Low Power FIR Filter Realization

@inproceedings{Portela2003OptimalCO, title={Optimal Combination of Number of Taps and Coefficient Bit-Width for Low Power FIR Filter Realization}, author={Jo{\~a}o Portela and Eduardo Costa and Jos{\'e} C. Monteiro}, year={2003} }

This paper addresses the optimization of FIR filters for low power. We propose a search algorithm to find the combination of the number of taps and coefficient bit-width that leads to the minimum number of total partial sums, and hence to the least power consumption. We show that the minimum number of taps does not necessarily lead to the least power consumption in fully parallel FIR filter architectures. This is particularly true if the reduction of the bit-width of the coefficients is taken… Expand

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#### 7 Citations

An improved synthesis method for low power hardwired FIR filters

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- Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)
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The results show significant reduction in the number of adders and logic depth of the multiplier block with a minimal degradation in the filter transfer characteristics, showing the usefulness of the proposed method for low power design of parallel filters. Expand

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It is shown that it is possible to achieve area savings for both, ASIC or FPGAs implementation and common sub-expression elimination among multipliers in constant coefficients parallel FIR filter optimizations. Expand

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FPGA implementation of Finite Impulse Response (FIR) filters using Distributed Arithmetic (DA) which substitute multiply and accumulate operations with a series of Look-Up-Table (LUT) accesses is discussed. Expand

Design Optimization Techniques Evaluation for High Performance Parallel FIR Filters in FPGA

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This paper presents synthesis results on a method t o minimize the amount of hardware needed to implement a parallel digital finite impulse response (FIR) filt ers for hardwired (fixed coefficients)… Expand

A power-predictive environment for fast and power-aware ASIC-based FIR filter design

- Engineering, Computer Science
- 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI)
- 2017

The main results show that the proposed power-predictive environment enables a fast and power-aware decision even in mathematical design level enabling saves in power dissipation with better filter quality, and also enabling a reduction in the time-to-market, which nowadays is a very important requirement. Expand

A High Performance Parallel FIR Filters Generation Tool

- Computer Science
- Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)
- 2006

This paper presents generation tool and performance results on a method to minimize the amount of hardware needed to implement a parallel digital finite impulse response (FIR) filters for hardwired… Expand

A VHDL Generation Tool for Optimized Parallel FIR Filters

- Computer Science
- 2006 IFIP International Conference on Very Large Scale Integration
- 2006

The generation tool employs a combination of two approaches: first, the reduction of the coefficients to n-power-of-two (NPT) terms, using cannonical signed digit (CSD) as an option, followed by common subexpression elimination among multipliers. Expand

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