Optimal Clock Period FPGA Technology Mapping for Sequential Circuits

@inproceedings{Pan1996OptimalCP,
  title={Optimal Clock Period FPGA Technology Mapping for Sequential Circuits},
  author={Peichen Pan and C. L. Liu},
  booktitle={DAC},
  year={1996}
}
In this paper, we study the technology mapping problem for sequential circuits for LUTbased FPGAs. Existing approaches map the combinational logic between ipops (FFs) while assuming the positions of the FFs are xed. We study in this paper a new approach to the problem, in which retiming is integrated into the technology mapping process. We present a polynomial time technology mapping algorithm that can produce a mapping solution with the minimum clock period while assuming FFs can be… CONTINUE READING
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