A low parasitic inductance ground for SiGe power amplifiers has been realized using a deep silicon via (DSV). The inductance of the DSV is approximately one order of magnitude smaller than the thru-wafer-via (TWV) inductance of ∼21 pH [1] enabling a ground path for power amplifiers in common emitter configuration with literally no parasitic inductance. In… (More)

Determining the Inductance of a Through- Substrate Via Using Multiple On-Wafer Test Approaches,

R. Uscola, M. Tutt

ICMTS Proceedings,

2001

2 Excerpts

Pucel, “Modeling Via Hole Grounds in Microstrip,

R. M. Goldfarb

IEEE Microwave and Guided Wave Letters,

1991

1 Excerpt

Determining the Inductance of a Through - Substrate Via Using Multiple On - Wafer Test Approaches An Accurate Calculation of Spreading Resistance Modeling Via Hole Grounds in Microstrip