On the reliability of performance counters for power models

Abstract

Modern processors have been equipped with Hardware Performance Counters (HPCs) and Performance Monitoring Units (PMUs) to keep track of hardware events, building adequate tools to debug and analyze systems. Recent research projects addressed the problem of building processor power models by correlating variations on power to hardware events. Here, we intent… (More)

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Cite this paper

@inproceedings{Hoeller2013OnTR, title={On the reliability of performance counters for power models}, author={Arliones Hoeller and Giovani Gracioli and Ant{\^o}nio Augusto Fr{\"{o}hlich}, year={2013} }