On the optimal design of triple modular redundancy logic for SRAM-based FPGAs


Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can… (More)
DOI: 10.1109/DATE.2005.229


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