On the decreasing significance of large standard cells in technology mapping

@inproceedings{Seo2008OnTD,
  title={On the decreasing significance of large standard cells in technology mapping},
  author={Jae-sun Seo and Igor L. Markov and Dennis Sylvester and David Blaauw},
  booktitle={ICCAD 2008},
  year={2008}
}
Technology scaling reduces gate delays while wire delays may increase. Our work studies the interaction of this phenomenon with technology mapping and its impact on modern EDA flows. In particular, we demonstrate that the use of larger standard cells increases the number of long wires and may undermine circuit delay optimization at 65 nm and below. Experiments with 130 nm, 90 nm, 65 nm, and 45 nm industrial CMOS technology suggest that limiting the use of larger standard cells in technology… CONTINUE READING

Results and Topics from this paper.

Key Quantitative Results

  • Experiments with 130 nm, 90 nm, 65 nm, and 45 nm industrial CMOS technology suggest that limiting the use of larger standard cells in technology mapping becomes more effective at 65 nm and 45 nm node, resulting in up to 12% improvement in critical path delay on large benchmark circuits.

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