On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays


A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous article is replaced by a time domain algorithm through a detailed comparison of their VLSI implementations. A new architecture that implements the time domain algorithm permits efficient pipeline processing with reduced circuitry. Erasure… (More)
DOI: 10.1109/12.5988

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