• Corpus ID: 13971832

On the Simulation of Time-Triggered Systems on a Chip with BIP

@article{Blech2011OnTS,
  title={On the Simulation of Time-Triggered Systems on a Chip with BIP},
  author={Jan Olaf Blech and Beno{\^i}t Boyer and Thanh-Hung Nguyen},
  journal={ArXiv},
  year={2011},
  volume={abs/1109.5505}
}
In this report, we present functional models for software and hardware components of Time-Triggered Systems on a Chip (TTSoC). These are modeled in the asynchronous component based language BIP. We demonstrate the usability of our components for simulation of software which is developed for the TTSoC. Our software comprises services and an application part. Our approach allows us to simulate and validate aspects of the software system at an early stage in the development process and without the… 
1 Citations
Towards a Formalization of the OSGi Component Framework
TLDR
A formalization of the OSGi component framework is presented and its use for behavioral types is described, intended to be used as a basis for describing behavior of OSGi based systems.

References

SHOWING 1-10 OF 16 REFERENCES
Concepts of Switching in the Time-Triggered Network-on-Chip
  • C. Paukovits, H. Kopetz
  • Computer Science
    2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
  • 2008
TLDR
The design of the switching components that make up the network-on-chip (NoC), as well as the switching algorithm applied in those components, are presented and the implications for the operation of the TTNoC entailed by these design choices are focused on.
Modeling Heterogeneous Real-time Components in BIP
  • A. Basu, M. Bozga, J. Sifakis
  • Computer Science
    Fourth IEEE International Conference on Software Engineering and Formal Methods (SEFM'06)
  • 2006
TLDR
The BIP language for the description and composition of layered components as well as associated tools for executing and analyzing components on a dedicated platform and provides a powerful mechanism for structuring interactions involving rendezvous and broadcast are presented.
The simulation semantics of SystemC
TLDR
The semantics of SystemC is presented in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation to help investigate SystemC interoperability with Verilog and VHDL.
The SAE Architecture Analysis & Design Language (AADL) a standard for engineering performance critical systems
  • P. Feiler, B. Lewis, S. Vestal
  • Computer Science
    2006 IEEE Conference on Computer Aided Control System Design, 2006 IEEE International Conference on Control Applications, 2006 IEEE International Symposium on Intelligent Control
  • 2006
The Society of Automotive Engineers (SAE) Architecture Analysis & Design Language, AS5506, provides a means for the formal specification of the hardware and software architecture of embedded computer
The IF Toolset
TLDR
The toolset is built upon a rich formalism, the IF notation, allowing structured automata-based system representations, and is expressive enough to support real-time primitives and extensions of high-level modelling languages such as SDL and UML by means of structure preserving mappings.
Verification of PLC Properties Based on Formal Semantics in Coq
TLDR
The proposed formal semantics of two languages defined in the IEC 61131-3 standard for PLC programming, a graphical high-level language that allows to describe the main control-flow of the system, and an associated tool for automatically generating SFC representations from a graphical description.
An Invariant Preserving Transformation for PLC Models
  • J. Blech, A. Hattendorf, Jia Huang
  • Computer Science
    2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops
  • 2011
TLDR
This work reports on a transformation from Sequential Function Charts and Function Block Diagrams of the IEC 61131 -- 3 standard to BIP, and establishes a notion of invariant preservation between the two languages.
Mapping Applications to Tiled Multiprocessor Embedded Systems
TLDR
The basic principles of the DOL, the specification mechanisms for applications, platform and mapping as well as its internal analytic performance evaluation framework are presented and an MPEG -2 decoder case study is presented.
D-Finder 2: Towards Efficient Correctness of Incremental Design
TLDR
The presented tool shares its theoretical roots with a previous implementation, but was completely rewritten to take advantage of a new version of BIP and various new results on the theory of invariant computation.
Metropolis: An Integrated Electronic System Design Environment
TLDR
Based on a metamodel with formal semantics that developers can use to capture designs, Metropolis provides an environment for complex electronic-system design that supports simulation, formal analysis, and synthesis.
...
...