Towards Feasible Implementations of Low-Latency Multi-writer Atomic Registers
In this work we conduct an experimental performance evaluation of four MWMR atomic register implementations: SFW from , APRX-SFW and CWFR from , and SIMPLE (the generalization of  in the MWMR environment). We implement the algorithms on NS2, a single processor simulator, and on PlanetLab, a planetary-scale real-time network platform. Due to its simplistic nature, SIMPLE requires two communication round-trips per read or write operation, but almost no local computation. The rest of the algorithms are (to this writing) the only to allow single round read and write operations but require non-trivial computational demands. We compare these algorithms with SIMPLE and amongst each other to study the trade-offs between communication delay and local computation. Our results shed new light on the practicality of atomic MWMR register implementations.