On the Operation Modes of Dual-Gate Reconfigurable Nanowire Transistors

@article{Sun2021OnTO,
  title={On the Operation Modes of Dual-Gate Reconfigurable Nanowire Transistors},
  author={Bin Sun and Benjamin Richstein and Patrick Liebisch and Thorben Frahm and Stefan Scholz and Jens Trommer and Thomas Mikolajick and Joachim Knoch},
  journal={IEEE Transactions on Electron Devices},
  year={2021},
  volume={68},
  pages={3684-3689}
}
We investigate the operation modes of a dual-gate reconfigurable field-effect transistor (RFET). To this end, dual-gate silicon-nanowire FETs are fabricated based on anisotropic wet etching of silicon and nickel silicidation yielding silicide-nanowire Schottky junctions at source and drain. We compare the program gate at source (PGAS) with the more usual program gate at drain (PGAD) operation mode. While in PGAD mode, ambipolar operation is suppressed, switching is deteriorated due to the… 
2 Citations

Figures from this paper

Logic and memory functions of an inverter comprising reconfigurable double gated feedback field effect transistors

In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode

An Electron Waveguide Model for FDSOI Transistors

We extend our previous semi-empirical model for quantum transport in a conventional nano-MOSFET to FDSOI transistors. In ultra-thin-body and -BOX (UTBB) FDSOI transistors, the electron channel can be

References

SHOWING 1-10 OF 27 REFERENCES

Top-Down Fabricated Reconfigurable FET With Two Symmetric and High-Current On-States

We demonstrate a top-down fabricated reconfigurable field effect transistor (RFET) based on a silicon nanowire that can be electrostatically programmed to p- and n-configuration. The device unites a

Top-Down Technology for Reconfigurable Nanowire FETs With Symmetric On-Currents

In this paper, a technology for top-down single-gated Schottky barrier transistor is presented exhibiting the highest symmetry of on-currents for n- and p-conductance of such

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

We fabricated and characterized new ambipolar silicon nanowire (SiNW) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. One gate electrode

Gate-Controlled WSe2 Transistors Using a Buried Triple-Gate Structure

Tungsten diselenide (WSe2) devices that can be tuned to operate as n-type and p-type field-effect transistors (FETs) as well as band-to-band tunnel transistors on the same flake, consistent with a simple estimation of the expected off-state behavior.

Reconfigurable silicon nanowire transistors.

This novel nanotransistor technology makes way for a simple and compact hardware platform that can be flexibly reconfigured during operation to perform different logic computations yielding unprecedented circuit design flexibility.

Quantum simulations of an ultrashort channel single-gated n-MOSFET on SOI

We present quantum mechanical simulations of a single-gated ultrashort channel MOSFET on silicon-on-insulator (SOI). Ballistic transport is assumed, in order to investigate ideal device performance.

Donor deactivation in silicon nanostructures.

It is shown that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in.

On the performance of single-gated ultrathin-body SOI Schottky-barrier MOSFETs

The authors study the dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness and show a performance improvement for decreasing SOI

Scaling the Si MOSFET: from bulk to SOI to bulk

Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer

Top-down fabrication of single crystal silicon nanowire using optical lithography

A method for fabricating single crystal silicon nanowires is presented using top-down optical lithography and anisotropic etching. Wire diameters as small as 10 nm are demonstrated using silicon on