On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects

@inproceedings{Murgan2007OnTN,
  title={On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects},
  author={Tudor Murgan and Petru Bogdan Bacinschi and Sujan Pandey and Alberto Garc{\'i}a Ortiz and Manfred Glesner},
  booktitle={PATMOS},
  year={2007}
}
In this work, the necessity of combining signal encoding schemes with low-level anti-crosstalk techniques like spacing and shielding is analyzed. It is shown that in order to increase the throughput improvement and/or reduce the power consumption, coding schemes should be integrated with layout techniques since methods like spacing and shielding can be regarded as very simple encoding schemes. On this basis, a theoretical framework for assessing the improvement in throughput and/or power… CONTINUE READING

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Showing 1-10 of 19 references

High-Level Optimization of Performance and Power in Very Deep Sub-Micron Technologies

T. Murgan
WiKu-Verlag, Duisburg–Cologne, Germany • 2007
View 3 Excerpts
Highly Influenced

Implementation of Delay and Power Reduction in Deep SubMicron Buses Using Coding

K. Konstantakopoulos
2002
View 3 Excerpts
Highly Influenced

Bus Stuttering : An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission

Proceedings of the Design Automation & Test in Europe Conference • 2006
View 1 Excerpt

Bus encoding for total power reduction using a leakage-aware buffer configuration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2005
View 1 Excerpt

Area and energy-efficient crosstalk avoidance codes for on-chip buses

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. • 2004
View 2 Excerpts

High-Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures

A. Garcı́a Ortiz, T. Murgan, L. D. Kabulepa, L. S. Indrusiak, M. Glesner
J. of Integrated Circuits and Systems 1(1), 23–31 • 2004
View 2 Excerpts

Interconnect-Centric Design for Advanced SoC and NoC

P. P. Sotiriadis
Power Reduction Coding for Buses, pp. 177–206. Kluwer, Dordrecht, The Netherlands • 2004

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