On the Effects of Process Variation in Network-on-Chip Architectures

@article{Nicopoulos2010OnTE,
  title={On the Effects of Process Variation in Network-on-Chip Architectures},
  author={Chrysostomos Nicopoulos and Suresh Srinivasan and Aditya Yanamandra and Dongkook Park and Narayanan Vijaykrishnan and Chita R. Das and Mary Jane Irwin},
  journal={IEEE Transactions on Dependable and Secure Computing},
  year={2010},
  volume={7},
  pages={240-254}
}
The advent of diminutive technology feature sizes has led to escalating transistor densities. Burgeoning transistor counts are casting a dark shadow on modern chip design: global interconnect delays are dominating gate delays and affecting overall system performance. Networks-on-Chip (NoC) are viewed as a viable solution to this problem because of their scalability and optimized electrical properties. However, on-chip routers are susceptible to another artifact of deep submicron technology… CONTINUE READING
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A speculative arbiter design to enable high-frequency many-VC router in NoCs

2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS) • 2013
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