On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits

@article{Weerasekera2010OnSO,
  title={On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits},
  author={Roshan Weerasekera and Matt Grange and Dinesh Pamunuwa and Hannu Tenhunen},
  journal={2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)},
  year={2010},
  pages={1325-1328}
}
This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not… CONTINUE READING