On polynomial-time testable classes of combinational circuits

Abstract

The problem of test generation for detecting stuck-at faults in combinational circuits is computationally intractable. Consequently, the identification of classes of circuits that support polynomial-time test generation algorithms is very important from testing and design viewpoints. The authors discuss several classes of polynomially-time testable circuits… (More)
DOI: 10.1109/VTEST.1991.208154

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Cite this paper

@article{Rao1991OnPT, title={On polynomial-time testable classes of combinational circuits}, author={Nageswara S. V. Rao and Shunichi Toida}, journal={Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's}, year={1991}, pages={172-177} }