On generating compact test sequences for synchronous sequential circuits

@inproceedings{Pomeranz1995OnGC,
  title={On generating compact test sequences for synchronous sequential circuits},
  author={Irith Pomeranz and Sudhakar M. Reddy},
  booktitle={EURO-DAC},
  year={1995}
}
We present a procedure to generate short test sequences for synchronous sequential circuits described at the gate level. Short test sequences are important in reducing test application time and memory requirements. The proposed procedure constructs a test sequence using a combination of fault-independent and faultoriented criteria. Experimental results are presented to demonstrate its effectiveness. 
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Generation for Synchronous Sequential Circuits

  • I. Pomeranz, S. M. Reddy, Test
  • Based on Fault Extraction",
  • 1991
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