On-chip segmented bus: a self-timed approach [SOC]

@article{Seceleanu2002OnchipSB,
  title={On-chip segmented bus: a self-timed approach [SOC]},
  author={Tiberiu Seceleanu and Juha Plosila and P. Lijeberg},
  journal={15th Annual IEEE International ASIC/SOC Conference},
  year={2002},
  pages={216-220}
}
Bus structure is one of the important issues within the present day system-on-chip design paradigm. Speed and power consumption characteristics of a bus-based device are highly dependent on the bus organization. We propose a segmented bus architecture which shows potential for improving both speed and power related figures of a bus-based system. From a globally asynchronous locally synchronous systems perspective, self-timed logic seems appropriate for interconnecting sub-systems operating at… CONTINUE READING

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