On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
@article{Dickson1976OnchipHG,
title={On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique},
author={J. Dickson},
journal={IEEE Journal of Solid-state Circuits},
year={1976},
volume={11},
pages={374-378}
}An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A… Expand
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