On-chip clock network skew measurement using sub-sampling


We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5 ps and a DNL of 1.2 ps. 


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@article{Das2008OnchipCN, title={On-chip clock network skew measurement using sub-sampling}, author={P. K. Das and Bharadwaj S. Amrutur and Jayanth Sridhar and V. Visvanathan}, journal={2008 IEEE Asian Solid-State Circuits Conference}, year={2008}, pages={401-404} }