On-chip Process Variation Detection and Compensation for Parametric Yield Enhancement in sub-100 nm CMOS technology

@inproceedings{Ghosh2007OnchipPV,
  title={On-chip Process Variation Detection and Compensation for Parametric Yield Enhancement in sub-100 nm CMOS technology},
  author={Amlan Ghosh and Rahul M. Rao and Richard B. Brown},
  year={2007}
}
The need for efficient compensation schemes to counter the impact of process variations on the parametric yield of designs has increased in the nm design era. In this paper, a process variation compensation technique that uses both delay and slew metrics has been proposed to determine the optimal NMOS and PMOS body-bias voltages to improve parametric yield… CONTINUE READING