On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)

@inproceedings{Sun2009OnchipPL,
  title={On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)},
  author={Quan Sun and Isabelle Valin and Christine Hu-Guo and Yu Hu and Kimmo Jaaskelainen and Gilles Claus},
  year={2009}
}
In a detector system, clock distribution to sensors must be controlled at a level allowing proper synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), we have proposed to distribute a low frequency clock at 10 MHz which will be multiplied to 160 MHz in each sensor by a PLL. A PLL has been designed for period jitter less than 20 ps rms, low power consumption and manufactured in a 0.35 μm CMOS process. 
A reticle size CMOS pixel sensor dedicated to the STAR HFT
ULTIMATE is a reticle size CMOS Pixel Sensor (CPS) designed to meet the requirements of the STAR pixel detector (PXL). It includes a pixel array of 928 rows and 960 columns with a 20.7 μm pixel

References

SHOWING 1-10 OF 12 REFERENCES
A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation
TLDR
The challenge was to design a phase-locked-loop (PLL) which combines limited jitter, low-supply voltage and low-power consumption.
Low-jitter and process independent DLL and PLL based on self biased techniques
  • J. Maneatis
  • Computer Science
    1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC
  • 1996
TLDR
This paper describes both a DLL and PLL design based upon self-biasing techniques in which all bias voltage and currents are referenced to other generated bias voltages and currents.
Precise delay generation using coupled oscillators
A new delay generator based on a series of coupled ring oscillators has been developed; it produces precise delays with subgate delay resolution for chip testing applications. It achieves a delay
A study of oscillator jitter due to supply and substrate noise
This paper investigates the timing jitter of single-ended and differential CMOS ring oscillators due to supply and substrate noise. We calculate the jitter resulting from supply and substrate noise,
A compensation strategy for two-stage CMOS opamps based on current buffer
The compensation with current buffer overcomes the typical drawbacks of the compensations based on nulling resistor or voltage buffer, but it is not as straightforward as the other two approaches.
STAR Vertex Detector Upgrade Development
TLDR
The basic detector requirements are presented, a sensor development path, conceptual mechanical design candidates and readout architecture are shown, and prototypes and beam test results with current generation MimoSTAR-2 sensors and a readout system featuring FPGA based on the fly hit finding and data sparsification are presented.
Vii. References
A comparative analysis of actuator technologies for robotics " , At low frequencies, performance is quite good The small downward spike corresponds to the lowest impedance that could be generated on
CMOS pixel sensor development: a fast read-out architecture with zero suppression
  • CMOS pixel sensor development: a fast read-out architecture with zero suppression
CMOS pixel sensor development: a fast read-out architecture with zero suppression, 2009 JINST 4 P04012doi: 10.1088/1748-0221/4/04/P04012
  • 2009
STAR vertex detector upgrade development, in Proceedings of Vertex 2007, Lake Placid
  • NY, U.S.A., September
  • 2007
...
1
2
...