On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

@article{Ker2004OnchipEP,
  title={On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process},
  author={Ming-Dou Ker and K.-H. Lin and Chien-Hui Chuang},
  journal={IEEE Transactions on Electron Devices},
  year={2004},
  volume={51},
  pages={1628-1635}
}
A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The… CONTINUE READING