On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization

  title={On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization},
  author={Vikram Iyengar and Krishnendu Chakrabarty and Erik Jan Marinissen},
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and exhaustive enumeration. However, this approach is computationally expensive for large SOCs, and it is limited to fixed-width test buses. We present… CONTINUE READING
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