On Synthesis of Combinational Logic Circuits

Sahadev Roy; C. Bhunia

DOI:10.5120/IJCA2015906311

Corpus ID: 3234215

On Synthesis of Combinational Logic Circuits

@article{Roy2015OnSO,
  title={On Synthesis of Combinational Logic Circuits},
  author={Sahadev Roy and C. Bhunia},
  journal={International Journal of Computer Applications},
  year={2015},
  volume={127},
  pages={21-26}
}

Sahadev Roy, C. Bhunia

Published 2015

Computer Science

International Journal of Computer Applications

Objective of this paper is to present historiography of logic switching circuits. The research mainly focuses on chronological development and application of logic in the field of electronic and computer applications. This paper briefly discussed on the basic needs of logic synthesis and also discuss few interesting facts and design consideration regarding logic synthesis. It also enhances student’s deep understanding of different logic function minimization technique during a lecture and… CONTINUE READING

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6 Citations

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References

SHOWING 1-10 OF 58 REFERENCES

SORT BY

The map method for synthesis of combinational logic circuits

M. Karnaugh
Mathematics
Transactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics
1953

Switching Theory for Logic Synthesis

T. Sasao
Computer Science
Springer US
1999

Multi-Level Logic Synthesis

T. Sasao
Computer Science
1999

An efficient equivalence checker for combinational circuits

Y. Matsunaga
Mathematics, Computer Science
DAC '96
1996

Constraints Analysis for Minimization of Multiple Inputs Logic Programming

NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis

Karl M. Fant, S. Brandt
Computer Science
Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96
1996