On Software Parallel Implementation of Cryptographic Pairings

@inproceedings{Grabher2008OnSP,
  title={On Software Parallel Implementation of Cryptographic Pairings},
  author={Philipp Grabher and Johann Gro{\ss}sch{\"a}dl and Dan Page},
  booktitle={IACR Cryptol. ePrint Arch.},
  year={2008}
}
A significant amount of research has focused on methods to improve the efficiency of cryptographic pairings; in part this work is motivated by the wide range of applications for such primitives. Although numerous hardware accelerators for pairing evaluation have used parallelism within extension field arithmetic to improve efficiency, thus far less emphasis has been placed on software exploitation of similar. In this paper we focus on parallelism within one pairing evaluation (intra-pairing… 
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Efficient Hardware Implementation of Fp-Arithmetic for Pairing-Friendly Curves
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A new method to speed up IFp-arithmetic in hardware for pairing-friendly curves, such as the well-known Barreto-Naehrig (BN) curves, using Montgomery reduction in a polynomial ring combined with a coefficient reduction phase using a pseudo-Mersenne number is described.
Highly-parallel hardware implementation of optimal ate pairing over Barreto-Naehrig curves
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
TLDR
This paper presents a design-space exploration of an application-specific instruction-set processor (ASIP) for the computation of various cryptographic pairings over Barreto-Naehrig curves (BN curves), and facilitates programming of the proposed ASIP by providing a C compiler.
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TLDR
It is argued in this paper that many real-world applications, such as server-side SSL/TLS handshake processing, would benefit more from throughput-optimized implementations than latencyoptimized ones.
Faster Pairing Coprocessor Architecture
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A high-speed pairing coprocessor using Residue Number System (RNS) which is intrinsically suitable for parallel computation and which outperforms all reported hardware and software designs.
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