On Optimal Tapering of FET Chains in High-Speed CMOS Circuits

@inproceedings{Ding2001OnOT,
  title={On Optimal Tapering of FET Chains in High-Speed CMOS Circuits},
  author={Li Ding and Pinaki Mazumder},
  year={2001}
}
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in high-performance circuit design with a view to minimizing the delay of a FET network. Currently, in a long FET network where MOS devices are stacked over one another to form a series chain network, the dimensions of the transistors are decreased from the bottom transistor to the top transistor in a manner where the width of transistors is tapered linearly or exponentially. However, it has… CONTINUE READING
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