On-Line Test Vector Generation from Temporal Constraints Written in PSL

@article{Oddos2006OnLineTV,
  title={On-Line Test Vector Generation from Temporal Constraints Written in PSL},
  author={Yann Oddos and Katell Morin-Allory and Dominique Borrione},
  journal={2006 IFIP International Conference on Very Large Scale Integration},
  year={2006},
  pages={397-402}
}
We propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a "foundation language" formula, we build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation 

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