On-Line Instruction-Checking in Pipelined Microprocessors


Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and… (More)
DOI: 10.1109/ATS.2008.47

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