On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic


An on-line error-detectable high-speed multiplier is described. It is based on the multiplication algorithm which we have previously proposed. In the algorithm, the redundant binary representation each of whose digits is 0, 1, or ¿1 is used. The multiplier consists of an input encoder, a multiplication block, and an error checker. The input encoder encodes… (More)
DOI: 10.1109/TC.1987.5009470


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