On Design and Application Mapping of a Network-on-Chip(NoC) Architecture

Abstract

As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to… (More)
DOI: 10.1142/S0129626408003363

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Cite this paper

@article{Bahn2008OnDA, title={On Design and Application Mapping of a Network-on-Chip(NoC) Architecture}, author={Jun Ho Bahn and Seung Eun Lee and Yoon Seok Yang and Jungsook Yang and Nader Bagherzadeh}, journal={Parallel Processing Letters}, year={2008}, volume={18}, pages={239-255} }