On-Chip Interconnection Architecture of the Tile Processor


......As the number of processor cores integrated onto a single die increases, the design space for interconnecting these cores becomes more fertile. One manner of interconnecting the cores is simply to mimic multichip, multiprocessor computers of the past. Following past practice, simple busbased shared-memory multiprocessors can be integrated onto a single piece of silicon. But, in taking this well-traveled route, we squander the unique opportunities afforded by single-chip integration. Specifically, buses require global broadcast and do not scale to more than about 8 or 16 cores. Some multicore processors have used 1D rings, but rings do not scale well either, because their bisection bandwidth does not increase with the addition of more cores. This article describes the Tile Processor and its on-chip interconnect network, iMesh, which is a departure from the traditional bus-based multicore processor. The Tile Processor is a tiled multicore architecture developed by Tilera and inspired by MIT’s Raw processor. A tiled multicore architecture is a multiple-instruction, multiple-data (MIMD) machine consisting of a 2D grid of homogeneous, general-purpose compute elements, called cores or tiles. Instead of using buses or rings to connect the many on-chip cores, the Tile Architecture couples its processors using five 2D mesh networks, which provide the transport medium for off-chip memory access, I/O, interrupts, and other communication activity. Having five mesh networks leverages the on-chip wiring resources to provide massive on-chip communication bandwidth. The mesh networks afford 1.28 terabits per second (Tbps) of bandwidth into and out of a single tile, and 2.56 Tbps of bisection bandwidth for an 8 3 8 mesh. By using mesh networks, the Tile Architecture can David Wentzlaff Patrick Griffin Henry Hoffmann Liewei Bao Bruce Edwards Carl Ramey Matthew Mattina Chyi-Chang Miao John F. Brown III Anant Agarwal

DOI: 10.1109/MM.2007.89

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@article{Wentzlaff2007OnChipIA, title={On-Chip Interconnection Architecture of the Tile Processor}, author={David Wentzlaff and Patrick Griffin and Henry Hoffmann and Liewei Bao and Bruce Edwards and Carl Ramey and Matthew Mattina and Chyi-Chang Miao and John F. Brown and Anant Agarwal}, journal={IEEE Micro}, year={2007}, volume={27}, pages={15-31} }