Corpus ID: 231503

On-Chip ESD Protection Design for Ics

@inproceedings{Feng2001OnChipEP,
  title={On-Chip ESD Protection Design for Ics},
  author={H. G. Feng and Ke Gong and R. Zhan and A. Wang},
  year={2001}
}
  • H. G. Feng, Ke Gong, +1 author A. Wang
  • Published 2001
  • This tutorial paper reviews the state of knowledge of on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits. The discussion covers critical issues in ESD design, such as, ESD test models, ESD failure mechanism, ESD protection structures, ESD device modeling, ESD simulation, ESD layout issues, and ESD influences on circuit functionality, etc. This review serves to provide industrial IC designers with a thorough and heady reference in dealing with ESD… CONTINUE READING
    2 Citations

    References

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