Corpus ID: 231503

On-Chip ESD Protection Design for Ics

  title={On-Chip ESD Protection Design for Ics},
  author={H. G. Feng and Ke Gong and R. Zhan and A. Wang},
  • H. G. Feng, Ke Gong, +1 author A. Wang
  • Published 2001
  • This tutorial paper reviews the state of knowledge of on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits. The discussion covers critical issues in ESD design, such as, ESD test models, ESD failure mechanism, ESD protection structures, ESD device modeling, ESD simulation, ESD layout issues, and ESD influences on circuit functionality, etc. This review serves to provide industrial IC designers with a thorough and heady reference in dealing with ESD… CONTINUE READING
    2 Citations


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    • H. Feng, Ke Gong, Albert Wang
    • Engineering
    • Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)
    • 2001
    • 5
    ESD in silicon integrated circuits
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    • Highly Influential
    A new design methodology using simulation for on-chip ESD protection designs for integrated circuits
    • Albert Wang, C. Tsay
    • Engineering
    • 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)
    • 1998
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    • Albert Wang
    • Engineering
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    • 2000
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    Basic ESD and I/O Design
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    On a dual-polarity on-chip electrostatic discharge protection structure
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    A comparison study of ESD protection for RFIC's: performance vs. parasitics
    • H. Feng, K. Gong, A. Wang
    • 2000 IEEE MTT-S International Microwave Symposium Digest (Cat. No.00CH37017)
    • 2000
    • 13