On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines

Abstract

Voltage droop is a major reliability concern in nano-scale very large-scale integration designs. Undesirable voltage droop is often a result of excessive IR drop. On the other hand, Ldi/dt-induced droop occurs when logic gates in the circuit draw high-switching current from the on-chip power supply network, and this problem is exacerbated at high-clock… (More)
DOI: 10.1109/TCAD.2015.2474392

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