On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology

@article{Roberts2007OnChipCD,
  title={On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology},
  author={David J Roberts and Nam Sung Kim and Trevor N. Mudge},
  journal={10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)},
  year={2007},
  pages={570-578}
}
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of current technologies, which is highly anticipated in processor on-chip caches manufactured with future nanometer scale technologies. Our most significant finding from this study is that the devices in on-chip memory cells cannot be scaled at the same rate as devices in logic circuits due to the increasing number of… CONTINUE READING
Highly Cited
This paper has 79 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 58 extracted citations

80 Citations

01020'09'12'15'18
Citations per Year
Semantic Scholar estimates that this publication has 80 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-9 of 9 references

Dynamic databit memory built - in self - repair

  • E. Hallnor N. Binkert
  • Int ’ l Conf . on Computer Aided Design ( ICCAD )
  • 2003

Decoding binary BCH codes

  • J. Komo
  • IEEE Trans . on Computers
  • 1993

Performance implications of tolerating cache faults

  • S. Mukhopadhyay
  • IEEE Trans . on Computers
  • 1993

Similar Papers

Loading similar papers…