## A New Family of High.Performance Parallel Decimal Multipliers

- Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi
- 18th IEEE Symposium on Computer Arithmetic (ARITH…
- 2007

@inproceedings{Shrivastava2016OnBT, title={On Binary to Bcd Converter for Decimal Adder}, author={Poornima Shrivastava and Prof. Balram Yadav}, year={2016} }

- Published 2016

Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. Binary to BCD conversion forms the basic building block of decimal digit adder. This paper presents novel high speed low power architecture for binary to BCD conversion which provides better results in terms of power, area, and delay than the existing designs of binary to BCD converter.