On Automated Feedback-Driven Data Placement in Multi-tiered Memory

  title={On Automated Feedback-Driven Data Placement in Multi-tiered Memory},
  author={T. Chad Effler and Adam P. Howard and Tong Zhou and Michael R. Jantz and Kshitij A. Doshi and Prasad A. Kulkarni},
Recent emergence of systems with multiple performance and capacity tiers of memory invites a fresh consideration of strategies for optimal placement of data into the various tiers. This work explores a variety of cross-layer strategies for managing application data in multi-tiered memory. We propose new profiling techniques based on the automatic classification of program allocation sites, with the goal of using those classifications to guide memory tier assignments. We evaluate our approach… 

MemBrain: Automated Application Guidance for Hybrid Memory Systems

MemBrain is introduced, a new memory management framework that automates the production and use of data-tiering guidance for applications on hybrid memory systems and can achieve significant performance and efficiency improvements compared to current guided and unguided management strategies.

Performance Potential of Mixed Data Management Modes for Heterogeneous Memory Systems

It is demonstrated that the mixed data management mode achieves the same or better performance than the best stand-alone option for five memory intensive benchmark applications (run separately and in isolation), resulting in an average speedup compared to the bestStand-alone policy of over 10 %, on average.

Profile-guided scope-based data allocation method

A new profile-guided scope-based approach is proposed which reduces the data allocation problem complexity, thus enhancing the precision of state of the art analyzes and evaluating the method on several benchmarks.

Application source code Annotated executable Memory usage statistics Program input Program execution Compile with site annotations MemBrain runtime Annotated executable Architectural profiling Site →

MemBrain is introduced, a new memory management framework that automates the production and use of data-tiering guidance for applications on hybrid memory systems and can achieve significant performance and efficiency improvements compared to current guided and unguided management strategies.

Crystal Gazer

Garbage collection in managed languages is used to exploit NVM capacity while preventing NVM wear out in hybrid memories with no changes to the programming model, and a Pareto tradeoff between DRAM usage and NVM lifetime is exposed.

Crystal Gazer: Profile-Driven Write-Rationing Garbage Collection for Hybrid Memories

Experimental results on an emula- tion platform show that Crystal Gazer eliminates the performance overhead of dynamic monitoring, while reducing more NVM writes than state-of-the-art write-rationing garbage collectors.

Valence: variable length calling context encoding

A new compiler-based strategy that significantly reduces the length of calling context encoding with little or no impact on instrumentation costs for many applications and leverages static analysis and variable length instrumentation to record each piece of the calling context using only a small number of bits.



Automating the Application Data Placement in Hybrid Memory Systems

The results of the evaluation reveal that the proposal is able to identify the key objects to be promoted into fast on-package memory in order to optimize performance, leading to even surpassing hardware-based solutions.

RTHMS: a tool for data placement on hybrid memory system

This work argues that intelligent, fine-grained data placement can achieve higher performance than default setups and presents an algorithm for data placement on hybrid-memory systems, based on a set of single-object allocation rules and global data placement decisions.

Cross-layer memory management for managed language applications

The design and implementation of this framework is described, which is the first to integrate automatic object profiling and analysis at the application layer with fine-grained management of memory hardware resources in the operating system, and it achieves its test goal of significant DRAM energy savings.

Data tiering in heterogeneous memory systems

The contribution of this paper is the design and implementation of a set of libraries and automatic tools that enables programmers to achieve optimal data placement with minimal effort on their part and shows that it is indeed possible to use a mix of a small amount of fast DRAM and large amounts of slower NVM without a proportional impact to an application's performance.

Utility-Based Hybrid Memory Management

While the memory footprints of cloud and HPC applications continue to increase, fundamental issues with DRAM scaling are likely to prevent traditional main memory systems, composed of monolithic

Thermostat: Application-transparent Page Management for Two-tiered Main Memory

This work presents Thermostat, an application-transparent huge-page-aware mechanism to place pages in a dual-technology hybrid memory system while achieving both the cost advantages of two-tiered memory and performance advantages of transparent huge pages, and implements and evaluates its effectiveness on representative cloud computing workloads running under KVM virtualization.

Traffic management: a holistic approach to memory placement on NUMA systems

The design of Carrefour is presented, the challenges of implementing it on modern hardware are presented, and insights about hardware support that would help optimize system software on future NUMA systems are drawn.

User Extensible Heap Manager for Heterogeneous Memory Platforms and Mixed Memory Policies

Software is proposed that will enable fine-grained client control over memory properties through the User Extensible Heap Manager, which efficiently reuses memory modified by expensive system calls and remains effective in a highly threaded environment.

Page Placement Strategies for GPUs within Heterogeneous Memory Systems

This work proposes two new page placement policies that improve GPU performance: one application agnostic and one using application profile information, and builds upon BW-AWARE placement by developing a compiler-based profiling mechanism that provides programmers with information about GPU application data structure access patterns.

A Survey Of Techniques for Architecting DRAM Caches

A survey of techniques for architecting DRAM caches is presented, by classifying these techniques across several dimensions, to underscore their similarities and differences.