On Acceleration of SAT-Based ATPG for Industrial Designs

@article{Drechsler2008OnAO,
  title={On Acceleration of SAT-Based ATPG for Industrial Designs},
  author={Rolf Drechsler and Stephan Eggersgl{\"u}{\ss} and G{\"o}rschwin Fey and Andreas Glowatz and Friedrich Hapke and J{\"u}rgen Schl{\"o}ffel and Daniel Tille},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2008},
  volume={27},
  pages={1329-1333}
}
Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation, relevant information about the problem might get lost and, therefore, is not available in the… CONTINUE READING

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