Offset Analysis and Design Optimization of a Dynamic Sense Amplifier for Resistive Memories

Abstract

The input-referred offset of a dynamic latch-based sense amplifier for resistive memories is extensively analyzed. This circuit is modeled using both small and large signal analysis, in order to evaluate mismatch effects and to support design robustness to process variations. Effect of various design parameters on offset are studied and reported. It is… (More)
DOI: 10.1109/ISVLSI.2017.64

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