Corpus ID: 16709149

OWER E FFICIENT D ESIGN OF M ULTIPLEXER USING A DIABATIC L OGIC

@inproceedings{Singh2013OWEREF,
  title={OWER E FFICIENT D ESIGN OF M ULTIPLEXER USING A DIABATIC L OGIC},
  author={R. Singh and R. Mehra},
  year={2013}
}
  • R. Singh, R. Mehra
  • Published 2013
    • This paper provides low power solutions for Very Large Scale Integration design. The dynamic power consumption of CMOS circuits is rapidly becoming a major concern in VLSI design. By adiabatic technique dynamic power consumption in pull up network can be reduced and energy stored on the load capacitance can be recycled. In this paper different logic style multiplexes have been analyzed and low power 2:1 multiplexer is designed using positive feedback adiabatic logic. It has been observed that… CONTINUE READING

    References

    SHOWING 1-10 OF 26 REFERENCES
    An Efficient Design of 2:1 Multiplexer and Its Application in 1-Bit Full Adder Cell
    • 6
    • Highly Influential
    Design Methodology for High Speed and Low Power Digital Circuits with Energy Economized Pass-transistor Logic (EEPL)
    • 12
    Power and Delay Analysis of a 2-to-1 Multiplexer Implemented in Multiple Logic Styles for Multiplexer-Based Decoder in Flash ADC
    • 15
    • Highly Influential
    Comparative Analysis of Adiabatic Compressor Circuits for Ultra-low Power DSP Application
    • 4
    Charge-recovery computing on silicon
    • 68
    2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic
    • 58
    • PDF
    Energy recovery performance of quasi-adiabatic circuits using lower technology nodes
    • V. S. K. Bhaaskaran
    • Engineering
    • India International Conference on Power Electronics 2010 (IICPE2010)
    • 2011
    • 25
    Low-power logic styles: CMOS versus pass-transistor logic
    • 964
    • PDF
    Analysis of Several 2:1 Multiplexer Circuits at 90nm and 45nm Technologies
    • 15
    • Highly Influential
    • PDF
    Input Selection Encoding for Low Power Multiplexer Tree
    • 13