Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU

@article{Abe2012NovelHD,
  title={Novel hybrid DRAM/MRAM design for reducing power of high performance mobile CPU},
  author={Keiko Abe and Hiroki Noguchi and E. Kitagawa and Naoharu Shimomura and Junichi Ito and Shinobu Fujita},
  journal={2012 International Electron Devices Meeting},
  year={2012},
  pages={10.5.1-10.5.4}
}
This paper presents novel DRAM/MRAM hybrid memory design that enables effective power reduction for high performance mobile CPU. Power reduction by about 60% of SRAM-based cache while application is running can be achieved with D-MRAM-based cache memory in CPU. This result is attributable to both novel D-MRAM memory design and lowest programming energy, 0.09pJ, of advanced p-MTJ with ultra-high speed write and low power write (3ns, 50uA). 
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