Novel high speed vedic mathematics multiplier using compressors

@article{Huddar2013NovelHS,
  title={Novel high speed vedic mathematics multiplier using compressors},
  author={S. Huddar and S. R. Rupanagudi and M. Kalpana and S. Mohan},
  journal={2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)},
  year={2013},
  pages={465-469}
}
  • S. Huddar, S. R. Rupanagudi, +1 author S. Mohan
  • Published 2013
  • Mathematics
  • 2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)
With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach… Expand

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