# Novel high speed vedic mathematics multiplier using compressors

@article{Huddar2013NovelHS, title={Novel high speed vedic mathematics multiplier using compressors}, author={S. Huddar and S. R. Rupanagudi and M. Kalpana and S. Mohan}, journal={2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)}, year={2013}, pages={465-469} }

With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach… Expand

#### 90 Citations

Novel High Speed Vedic Mathematics Multiplier using Compressors

- 2015

With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the… Expand

Fast Fourier Transform utilizing Modified 4 : 2 & 7 : 2 Compressor

- 2015

With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well-known fact that the… Expand

Design of High Speed 32 Bit Multiplier Architecture Using Vedic Mathematics and Compressors

- 2015

Multiplier unit is the key block of digital signal processors as well as general purpose processors that substantially decide the speed of processor. Design of high speed multiplier is need of the… Expand

Design of High Speed Multiplier using Vedic Mathematics

- Mathematics
- 2014

With the advancement of technology, a processor is required to have high speed. Multiplication is a critical operation of Digital Signal processing(DSP) applications(like DFT, FFT, convolution etc),… Expand

High Speed 16 Bit Digital Multiplier Architecture Using Urdhwa Tiryakbhyam and Compressors

- 2015

With the growing technology in field of Communication and VLSI a very high Speed processing power and low area is area is required. Multiplier unit is the central part of digital signal processor as… Expand

A Novel VLSI Architecture for FFT Utilizing Proposed 4:2 & 7:2 Compressor

- Engineering
- 2015

With the appearance of new innovation in the fields of VLSI and correspondence, there is likewise a perpetually developing interest for fast transforming and low range outline. It is likewise a… Expand

High Speed and Area Efficient Narrow Band Filter based on Compressor

- 2016

In this paper, we present the design optimization of high speed area efficient narrow band filter (NBF) sing compressor based multiplier. With the advent of new technology in the fields of VLSI and… Expand

Low Area and High Speed Vedic Mathematics Multiplier using Compressor

- Mathematics
- 2015

There is a growing demand for high speed processing and low area design for VLSI and Communication applications in recent days. The integral part of the processor is the multiplier. The multiplier is… Expand

High speed vedic multiplier designs-A review

- Mathematics
- 2014 Recent Advances in Engineering and Computational Sciences (RAECS)
- 2014

Multipliers are the key block in high speed arithmetic logic units, multiplier and accumulate units, digital signal processing units etc. With the increasing constraints on delay, more and more… Expand

High speed Vedic multiplier design and implementation on FPGA

- Computer Science
- 2015

Compressor based Vedic Multipliers show considerable improvements in speed and area efficiency. Expand

#### References

SHOWING 1-10 OF 15 REFERENCES

High speed energy efficient ALU design using Vedic multiplication techniques

- Computer Science
- 2009 International Conference on Advances in Computational Tools for Engineering Applications
- 2009

The efficiency of Urdhva Triyagbhyam-Vedic method for multiplication is proved which strikes a difference in the actual process of multiplication itself, which enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm. Expand

Design and implementation of two variable multiplier using KCM and Vedic Mathematics

- Mathematics, Computer Science
- 2012 1st International Conference on Recent Advances in Information Technology (RAIT)
- 2012

A novel multiplier architecture based on ROM approach using Vedic Mathematics is proposed, which is similar to that of a Constant Co-efficient Multiplier (KCM), but for KCM one input is to be fixed, while the proposed multiplier can multiply two variables. Expand

Low cost serial multipliers for high-speed specialised processors

- Mathematics
- 1988

This paper presents four new arrays for signed number multiplication and multiplication/ addition. In these structures, it is assumed that the factors are expressed in 2's complement while the addend… Expand

Multiplier design based on ancient Indian Vedic Mathematics

- Mathematics
- 2008 International SoC Design Conference
- 2008

Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). It mainly deals with Vedic… Expand

Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers

- Mathematics
- 1998

A 3-2 counter and a 4-2 compressor are the basic components in the partial product summation tree of a parallel array multiplier. A new high-speed and low power design of these components is… Expand

Low power CMOS pass logic 4-2 compressor for high-speed multiplication

- Mathematics
- Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)
- 2000

A novel CMOS 4-2 compressor using pass logic is presented in this paper. An XOR-XNOR combination gate is used to build the circuit while totally eliminating the use of inverters. The total power… Expand

An efficient method of elliptic curve encryption using Ancient Indian Vedic Mathematics

- Computer Science
- 48th Midwest Symposium on Circuits and Systems, 2005.
- 2005

Efficient hardware circuitry for point doubling using square algorithms of Ancient Indian Vedic Mathematics, "Duplex" D property of binary numbers is proposed in order to calculate the square of a number. Expand

A Two's Complement Parallel Array Multiplication Algorithm

- Mathematics, Computer Science
- IEEE Transactions on Computers
- 1973

An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described, which is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit. Expand

Computer arithmetic algorithms

- Computer Science
- 1993

The principles of the algorithms available for performing arithmetic operations in digital computers, described independently of specific implementation technology and within the same framework, are explained. Expand