Novel Viterbi decoder VLSI implementation and its performance

@article{Kubota1993NovelVD,
  title={Novel Viterbi decoder VLSI implementation and its performance},
  author={S. Kubota and Shuzo Kato and Tsunehachi Ishitani},
  journal={IEEE Trans. Commun.},
  year={1993},
  volume={41},
  pages={1170-1178}
}
An advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation is presented. Two novel circuit design schemes have been proposed: scarce state transition (SST) decoding and direct high-coding-rate convolutional code generation and variable-rate decoding. SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading error probability performance. Moreover, the power consumption of the SST Viterbi decoder is… 

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