Novel FPGA based Haar classifier face detection algorithm acceleration

@article{Gao2008NovelFB,
  title={Novel FPGA based Haar classifier face detection algorithm acceleration},
  author={Changjian Gao and Shih-Lien Lu},
  journal={2008 International Conference on Field Programmable Logic and Applications},
  year={2008},
  pages={373-378}
}
We present here a novel approach to use FPGA to accelerate the Haar-classifier based face detection algorithm. With highly pipelined microarchitecture and utilizing abundant parallel arithmetic units in the FPGA, wepsilave achieved real-time performance of face detection having very high detection rate and low false positives. Moreover, our approach is flexible toward the resources available on the FPGA chip. This work also provides us an understanding toward using FPGA for implementing non… CONTINUE READING
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